\documentclass{beamer}

\usepackage[latin1]{inputenc}
\usepackage{xcolor}

\xdefinecolor{lavendar}{rgb}{0.9,1,0.95}
\xdefinecolor{teal}{rgb}{0.85,0.95,1}

\usepackage{tikz}
\usetikzlibrary{shapes,calc}

\beamertemplatenavigationsymbolsempty

\usetheme{Warsaw}
\usecolortheme{whale}

\usefonttheme{structurebold}

\begin{document}
\title	{Microprocessor project: Digital watch} 
\date{\small 2009-2010: Semester 1}
\author{Fabrice Ben Hamouda, Yoann Bourse, Hang Zhou}



\begin{frame}[plain]
\begin{center}
\textsc{Digital System}
\end{center}
\titlepage
\end{frame}

\begin{frame}\frametitle{Table of contents}\tableofcontents
\end{frame} 















\section{Netlists and simulator} 
\subsection{Netlists}
\begin{frame}\frametitle{Netlist language} 
\begin{itemize}
\item Very \alert{simple}
\item Inspired by the course and the instructions
\item Easily manipulable by the teachers
\end{itemize}
\vspace{0.4cm}

\begin{exampleblock}{Examples}
\begin{columns}
\begin{column}{2cm}

o = clk2()\{	\\
\hspace{0.3cm} o=Z(c)\\
\hspace{0.3cm} c=\~\ Z(o)\\
\}\\

\end{column}
\begin{column}{5cm}

s,r = FullAdd(a,b,c)\{\\
\hspace{0.3cm} s = a\^\ b\^\ c\\
\hspace{0.3cm} r = (a \& b) $|$ ((a\^\ b) \& c)\\
\hspace{0.3cm} inst o = clk2 () \hspace{0.3cm} \textit{\# useless}\\
\}

\end{column}
\end{columns}
\end{exampleblock}
\end{frame}


\begin{frame}\frametitle{PHP Netlist language} 
\textbf{Drawback: } no high-level functions (loops, recursion...)\\
\vspace{0.2cm}
$\Rightarrow$ \textbf{Solution: } \alert{PHP as a Netlist generator}
\vspace{0.2cm}
\begin{itemize}
\item Easy mix of PHP code and netlist language
\item Netlists are true overview of real circuits
\end{itemize}
\end{frame}


\begin{frame}\frametitle{PHP Netlist language (example)} 

\begin{exampleblock}{Example}

m = main(\alert{$<?$=listV("a",0,\$m)$?>$},\alert{$<?$=listV("s",0,\$n)$?>$})\{\\
\hspace{0.2cm} inst m = mux3(\alert{$<?$=listV("a",0,\$m)$?>$},\alert{$<?$=listV("s",0,\$n)$?>$})\\
\}

\end{exampleblock}

\pause

\vspace{1cm}

\begin{exampleblock}{Gives for \$ m = 3 and \$ n = 5}

m = main(\alert{a[2],a[1],a[0]} , \alert{s[4],s[3],s[2],s[1],s[0]})\{\\
\hspace{0.2cm} inst m = mux3(\alert{a[2],a[1],a[0]} , \alert{s[4],s[3],s[2],s[1],s[0]})\\
\}

\end{exampleblock}
\end{frame}

\subsection{Specifications of the simulator}
\begin{frame}\frametitle{Specifications of the simulator}
Ability to set cycle frequency.

Two modes: 
\begin{itemize}
\item Simple interpretation
\item Compilation towards C++: circuits run like a program
\end{itemize} 
Outputs:
\begin{itemize}
\item Truthtable
\item Seven segments interface
\item Timing diagram
\end{itemize} 
\end{frame}

\subsection{Circuit watch}
\begin{frame}\frametitle{Circuit watch}
\begin{center}
\includegraphics[height=140pt]{circuitwatch.jpg}
\end{center}

$1^{st}$ watch: circuit watch (huge circuit) \\
$\Rightarrow$ \alert{Demonstration}

\end{frame}



\section{Global functionning}
\begin{frame}[plain]
\frametitle{Global functionning}

\includegraphics[height=215pt]{files.pdf}
\end{frame}


 
\section{Microprocessor}
\subsection{Instruction set - specifications}
\begin{frame}\frametitle{General presentation}
\alert{Close to MIPS} in order to use our OCAML Compiler.

\begin{itemize}
\item Harvard architecture \\(instruction bus separated from data bus).
\item One instruction per clock cycle.
\end{itemize}

\pause

\begin{alertblock}{Bus length, register length/number, ...}
All is 16 !
\end{alertblock}

\end{frame}

\begin{frame}\frametitle{General presentation}

\begin{itemize}
\item 16 registers of 16 bits
\item 16 bits instructions
\item Up to 64 K instructions (ROM) (16 bits address length)
\item Up to 2$\times$64 KB of data RAM (16 bits address/data length)
\end{itemize}

\end{frame}

\begin{frame}\frametitle{Special instructions/features}

\begin{itemize}
\item Up to 8 (\textit{+2 for the timer}) output ports and 8 (\textit{+2 for the timer}) input ports of 16 bits \\
$\longrightarrow$ controlled by \textit{input}/\textit{output} instructions.
\pause
\item \textit{Sleep} instruction
\pause
\item One 16 bits clock timer
\begin{itemize}
\item Incremented each clock cycle.
\item Timer period controlled by an output port.
\item Wake up microprocessor each time it reaches its period.
\end{itemize}
\end{itemize}

\end{frame}

\begin{frame}\frametitle{External interfaces}

\begin{center}
\renewcommand{\arraystretch}{1.8}
\begin{tabular}{|c|c|c|}
\hline  & \textbf{Input} & \textbf{Output} \\ 
\hline 0-7 & real 16 bits input port 0-7 & real 16 bits output port 0-7 \\ 
\hline 8 & \multicolumn{2}{c|}{16 bits timer \textit{period}} \\ 
\hline 9 & \multicolumn{2}{c|}{16 bits timer} \\
\hline 
\end{tabular} 
\end{center}

\end{frame}

\begin{frame}\frametitle{MIPS comparison}

\begin{center}
\renewcommand{\arraystretch}{1.5}
\begin{tabular}{|c|c|c|}
\hline           & \textbf{MIPS}                    & \textbf{Our microprocessor} \\ 
\hline \textbf{Registers} & 32 $\times$ 32 bits            & 16 $\times$ 16 bits \\ 
\hline \textbf{ALU}       & $+ \; - \;$ \alert{ $\times \; \div \; \mod$} & $+ \; -$ \\ 
                          & $\& \; | \; \oplus \; \ll \; \gg \; \mbox{not}$ & $\& \; | \; \oplus \; \ll \!\! 1 \; \mbox{not}$ \\
\hline \textbf{Conditional branch} & on a comparision     & \alert{last result} (zero, carry)  \\ 
\hline \textbf{Special instructions} & syscall & \alert{input, output, sleep} \\ 
\hline \textbf{Special features} & & 16 bits timer \\
\hline 
\end{tabular} 
\end{center}
\end{frame} 


\begin{frame}[plain]
\frametitle{Specifications}
\includegraphics[height=200pt]{microproc.pdf}
\end{frame}

\subsection{Assembly translator}
\begin{frame}\frametitle{Assembly translator}
Translates assembly code in machine language (integer instructions)
\begin{itemize}
\item Replace labels
\item Pseudoinstructions : (\textit{addui} : add a register with a literal)
\item Simulation in C
\end{itemize}
\end{frame}


\begin{frame}[containsverbatim]

\begin{exampleblock}{Example}
\begin{verbatim}

    li      W0  5       ; W0 <- 5
    
    output  0   W0      ; output W0=5 on port 0
	
	
    input   W1  1       ; read port 1 in W1
    
    addu    W1  W1  W0  ; W1 <- W1 + W0
    
    output  0   W1      ; output result on port 0
\end{verbatim}
\end{exampleblock}

\end{frame}


\subsection{Netlist realisation}
\begin{frame}\frametitle{Netlist realisation}
\includegraphics[height=100pt]{picture.pdf}
\end{frame}



\subsection{Assembly watch}
\begin{frame}\frametitle{Assembly watch}
$2^{nd}$ watch: assembly watch (slower) \\
$\Rightarrow$ \alert{Demonstration}
\end{frame}

\section{Results}

\subsection{Compilation}

\begin{frame}[allowframebreaks=0.90]\frametitle{Compilation}
Compile OCAML on our microprocessor thanks to MIni MOdules (MIMO) project:
\begin{itemize}
\item Add some OCAML functions (sleep, inputs, outputs)
\item Software multiplication, division, modulo
\item Software heap management
\item Conditional branch conversion
\item Terminal recursion management
\end{itemize}

\framebreak

Drawbacks:
\begin{itemize}
\item not very well optimized
\item longer code due to use of stack\\(manual watch: only registers !)
\item big assembly file (1299 line in generated assembly watch instead of 129 in manual assembly watch)
\end{itemize}

\framebreak

Advantages of OCAML (high level language):
\begin{itemize}
\item easy function call
\item automatic heap/stack management (for big project)
\item transparent use of software operation (multiplication, division)
\item easy debugging (just use OCAML executable)
\end{itemize}

\vspace{0.5cm}
$3^{rd}$ watch: OCAML watch\\
$\Rightarrow$ \alert{Demonstration}
\end{frame}

\subsection{Results overview}
\begin{frame}\frametitle{Results overview}

\begin{center}
\begin{tikzpicture}[font=\sffamily, scale=1, transform shape]
  \tikzstyle{c1Fill} = [fill=yellow!5]
  \tikzstyle{c1} = [draw=black, c1Fill,minimum width=3cm, minimum height=1cm, node distance=2cm]
  \tikzstyle{r1} = [draw=black, minimum width=4cm, minimum height=1cm,  node distance=2cm]
  \def\zh{2}
  \def\d2{-0.5}

  \node(H)[c1] {};
  \path (H.south)+(0,\d2) node (N)[c1] {Netlist};
  \path (N.south)+(0,\d2) node (A)[c1] {Asm};
  \path (A.south)+(0,\d2) node (O)[c1] {Ocaml};

  \path (H.east)+(\zh,0) node (H1)[r1,fill=black!5!white] {Compilation Mode};
  \path (H1.east)+(\zh,0) node (H2)[r1,fill=black!10!white] {Interpreting Mode};

  \path (N.east)+(\zh,0) node (N1)[r1,fill=red!10!white] {$6.0 \times 10^6$};
  \path (N1.east)+(\zh,0) node (N2)[r1,fill=red!18!white] {$1.5 \times 10^6$};

  \path (A.east)+(\zh,0) node (A1)[r1,fill=blue!10!white] {$0.96 \times 10^6$};
  \path (A1.east)+(\zh,0) node (A2)[r1,fill=blue!18!white] {$0.09 \times 10^6$};

  \path (O.east)+(\zh,0) node (O1)[r1,fill=green!10!white] {$0.96 \times 10^6$};
  \path (O1.east)+(\zh,0) node (O2)[r1,fill=green!18!white] {$0.10 \times 10^6$};

  \path (O.south)+(4,-0.5) node (diagramTitle)
    {Speed Comparison between Different Modes and Different Watches};
  \path (O.south)+(4,-1) node (diagramTitle)
    {Number of cycles simulated per minute};
\end{tikzpicture}
\end{center}

\end{frame}


\end{document}