\documentclass[10pt,a4paper]{article}
\usepackage[utf8x]{inputenc}
\usepackage{ucs}
\usepackage{amsmath}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{fullpage}
\usepackage{url}
\usepackage{graphicx}
\usepackage{xcolor}

\definecolor{border}{rgb}{0.3,0.3,0.3}
\definecolor{fonce}{rgb}{0.5,0.5,0.5}
\definecolor{fond}{rgb}{0.9,0.9,0.9}
\definecolor{b_class}{rgb}{0.0,0.25,0.1}
\definecolor{b_warning}{rgb}{0.25,0,0.1}
\definecolor{class}{rgb}{0.9,1,0.95}
\definecolor{warning}{rgb}{1,0.9,0.95}

\newcommand{\cbox}[1]{
	\vspace{8pt}
	\begin{center}%
	\fcolorbox{border}{fond}{%
	\begin{minipage}{0.8\textwidth}%
	#1%
	\end{minipage}%
	}%
	\end{center}%
}

\newcommand{\lbox}[1]{
	\vspace{8pt}
	\fcolorbox{fond}{fonce}{%
	\begin{minipage}{0.4\textwidth}%
	#1%
	\end{minipage}%
	}%
}

\newcommand{\bclass}[2]{
	\begin{flushright}%
	\textcolor{b_class}{\\\textbf{#1}} \\%
	\fcolorbox{b_class}{class}{%
	\begin{minipage}{0.8\textwidth}%
	#2%
	\end{minipage}%
	}%
	\end{flushright}%
	\vspace{5pt}
}


\newcommand{\instr}{\texttt}
\newenvironment{warning}{
\fcolorbox{b_warning}{warning}{
\textbf{Warning :}
}
}{}

\title	{	
		\normalsize Digital System - II \\
		\huge 	\textbf{Microprocessor}
		} 
\date{\small 2009-2010 : Semestre 1}
\author{Fabrice Ben Hamouda, Yoann Bourse, Hang Zhou}

\usepackage{ifpdf}

\ifpdf
\usepackage[pdftex, pagebackref=false, colorlinks=true, linkcolor=black, unicode]{hyperref}
\else
\usepackage[ps2pdf, pagebackref=false, colorlinks=true, linkcolor=black, unicode]{hyperref}
\fi 

\begin{document}
\maketitle
\tableofcontents
\newpage

We will now describe the specifications and features of the microprocessor we will be using to simulate a digital watch, thanks to the netlist simulator previously conceived. Assembly programs will be translated into digital instructions that the microprocessor will interpret in order to use correctly logical circuits for computation. The translation from assembly to machine language is performed by a program which is also able to simulate the expected results of the assembly code.

\section{Overview}

The main features of our microprocessor are :

\begin{itemize}
\item 16 registers of 16 bits
\item one 16 bits clock timer
\item 16 bits instructions
\item one instruction per clock cycle
\item up to 64 K instructions (ROM)
\item up to 2$\times$64 KB of data RAM (16 bits data length)
\item up to 8 (\textit{+2 for the timer}) output ports and 8 (\textit{+2 for the timer}) input ports of 16 bits
\end{itemize}

We chose to develop an architecture close to MIPS, because that is the microprocessor we use in the course ``Langage de programmation et compilation''.
Therefore, we hope to be able to combine this handmade microprocessor with the compiler we have to build for this course, so that we will have traced the whole path from CAML instruction to circuit execution. Some modifications will be needed to adapt the compiler : our microprocessor doesn't have multiplication or division instructions, and uses 16 bits integer instead of 32. Nevertheless, those changes will be minor because even if our microprocessor has fewer register and fewer instructions, the compiler will not use all MIPS registers and instructions, and most of the instructions we lack can be simulated by several of our instructions.
\subsection{Schema}

\begin{center}
\includegraphics[width=\textwidth]{microproc.png} 
\end{center}

\subsection{Registers}

There are 16 registers of 16 bits, labeled by integers : $W_0$ to $W_{15}$. You may use them the way you want, but we advise you to use the following conventions, inspired from MIPS conventions :

\begin{center}
\begin{tabular}{|c|c|c|}
\hline          & \textbf{MIPS equivalent} & \textbf{Usage} \\ 
\hline $W_{0}$  & \$V0 & expression evaluation and results of a function \\ 
\hline $W_{1}$  & \$V1 & expression evaluation and results of a function \\ 
\hline $W_{2}$  & \$A0 & argument 1 \\ 
\hline $W_{3}$  & \$A1 & argument 2 \\ 
\hline $W_{4}$  & \$A2 & argument 3 \\ 
\hline $W_{5}$  & \$A3 & argument 4 \\ 
\hline $W_{6}$  & \$S0 & saved temporary (preserved across call) \\ 
\hline $W_{7}$  & \$S1 & saved temporary (preserved across call) \\ 
\hline $W_{8}$  & \$S2 & saved temporary (preserved across call) \\ 
\hline $W_{9}$  & \$T0 & temporary (not preserved across call) \\ 
\hline $W_{10}$ & \$T1 & temporary (not preserved across call) \\ 
\hline $W_{11}$ & \$T2 & temporary (not preserved across call) \\ 
\hline $W_{12}$ & \$RA & return address \\ 
\hline $W_{13}$ & \$SP & stack pointer \\ 
\hline $W_{14}$ & \$FP & frame pointer \\ 
\hline $W_{15}$ & \$AT & temporary register used by pseudo-instruction (see \ref{pseudoinstr}) \\
\hline 
\end{tabular} 
\end{center}

Thanks to \instr{jmp*} instruction with two arguments (see instructions set, section \ref{instrset}), you can save return address in any register (instead of only $W_{15}$) when you jump to another point of the assembly program. That way, you can create functions calls. The mechanism is nearly the same as in MIPS architecture (see \cite{spim}) with \instr{jla} MIPS instruction.\\
Our microprocessor also uses two additional registers in conditional jumping, registers \textit{carry} and \textit{zero}, described below.


\subsection{\textit{Carry} and \textit{zero} registers}

One of the most important difference with MIPS architecture is the lack of conditional instructions like MIPS \instr{beq} (see \cite{spim}). This lack is compensated by two 1 bit pseudo-registers \textit{carry} and \textit{zero}. They are unaccessible to the user. They are automatically updated by most  instructions. We have some instructions providing jump conditioned on the value of those two registers.

\subsubsection{\textit{Carry} register}\label{carry}
\textit{Carry} register is only updated by arithmetic operations (\instr{addu}, \instr{subu}, \instr{sub}, \instr{sra}, \instr{srl} instructions, and pseudo-instructions which use these real instructions - see instructions set, section \ref{instrset}).

\begin{itemize}
\item \instr{addu} $W_{dst}$ $W_{src1}$ $W_{src2}$ : \textit{carry} will be set if $W_{src1}+W_{src2} \ge 2^{16}$ (values considered as unsigned)
\item \instr{subu} $W_{dst}$ $W_{src1}$ $W_{src2}$ : \textit{carry} will be set if $W_{src1}-W_{src2} \ge 0$ (values considered as unsigned)
\item \instr{sub~} $W_{dst}$ $W_{src1}$ $W_{src2}$ : \textit{carry} will be set if $W_{src1}-W_{src2} \ge 0$ (values considered as signed)
\item \instr{sra~} $W_{dst}$ $W_{src}$ : \textit{carry} is the less significant bit of $W_{src}$
\item \instr{sla~} $W_{dst}$ $W_{src}$ : \textit{carry} is the less significant bit of $W_{src}$
\end{itemize}

For example, suppose that $ W_0 = 10 $ and $ W_1 = -4 = 2^{16} - 4 $ :\\ %manual listing in order for the example not to steal the focus of the itemize
- \instr{addu} $W_2$ $W_0$ $W_1$ will set carry\\
- \instr{subu} $W_2$ $W_0$ $W_1$ will clear carry because $10 < 2^{16}-4$\\
- \instr{sub~}  $W_2$ $W_0$ $W_1$ will set carry because $10 \ge -4$\\

\subsubsection{\textit{Zero} register}
\textit{Zero} is updated after each instruction using a destination register ($W_{dst}$ in  \ref{instrset}.instruction set). If the new value of $W_{dst}$ is 0, \textit{zero} will be set, otherwise it will be cleared.\\
That way, you can easily jump if two registers are equal by jumping if the result of a \instr{xor} on those two register is 0.

\subsection{External interfaces}

Programs can communicate with other module of the CPU through \instr{input} and \instr{output} instructions. Here are the current mapping of address :

\begin{center}
\begin{tabular}{|c|c|c|}
\hline  & \textbf{Input} & \textbf{Output} \\ 
\hline 0-7 & real 16 bits input port 0-7 & real 16 bits output port 0-7 \\ 
\hline 8 & \multicolumn{2}{c|}{16 bits timer \textit{period}} \\ 
\hline 9 & \multicolumn{2}{c|}{16 bits timer} \\
\hline 
\end{tabular} 
\end{center}

Default values are 0.

\subsection{Timer and sleep mode}\label{sleep}

Our microprocessor has a 16 bits timer, that is to say a counter modulo \textit{period} incremented at each clock cycle. A 0 \textit{period} corresponds to a counter modulo $2^{16}$ (default). You can set its period and its value with \instr{input} and \instr{output} instructions (see above).

\begin{warning}
If you change the period to a value less than or equal to current timer value, the counter will not be reset. Hence it is recommended to manually reset counter (by setting it to 0) after changing its period.
\end{warning} \\

You can put microprocessor into \textit{sleep} mode with \instr{sleep} instruction. Nothing is done until the timer reaches its period.
This feature is important for the digital watch, because we need to increment seconds with the good period.

\section{Instructions set}\label{instrset}

You will find below the set of instructions used by our microprocessor. Assembly programs used with our translator can use real microprocessor instructions or pseudo-instructions that will be converted into several real instructions by the translator.\\

We will use the following notations :
\\
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
 $W_{x}$ & register $W_x$ & \\ \hline
K ($n$) & constant of $n$ bits  &      4, 8 or 16 bits \\ \hline
\textit{lo}(*) & low bits (half) of *    &   4 or 8 bits\\ \hline
\textit{hi}(*) & high bits (half) of *   &   4 or 8 bits \\ \hline

addr(label) & address of the label & 16 bits \\\hline
\end{tabular}
\end{center}

\subsection{Real instructions}

Here are real instructions, the four last columns displaying the instruction code saved in a ROM program.


\begin{center}
\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|}
\hline \multicolumn{9}{|c|} {\bfseries ALU instructions} \\ \hline

&&&&&\multicolumn{4}{|c|}{4$\times$4 bits} \\ \hline

\instr{addu}  & $W_{dst}$ & $W_{src1}$ & $W_{src2}$ & $W_{dst} \leftarrow W_{src1} + W_{src2}$
& 0 & dst & src1 & src2 \\ \hline
\instr{adduc} & $W_{dst}$ & $W_{src1}$ & $W_{src2}$ & $W_{dst} \leftarrow W_{src1} + W_{src2} + carry$
& 1 & dst & src1 & src2\\ \hline

\instr{subu}\footnotemark[1]  &$W_{dst}$&$W_{src1}$&$W_{src2}$&$W_{dst} \leftarrow  W_{src1} - W_{src2}$
& 2 & dst & src1 & src2\\ \hline
\instr{sub}\footnotemark[1] &$W_{dst}$&$W_{src1}$&$W_{src2}$&$W_{dst} \leftarrow  W_{src1} - W_{src2}$
& 3 & dst & src1 & src2\\ \hline

\instr{xor} &$W_{dst}$&$W_{src1}$&$W_{src2}$&$W_{dst} \leftarrow  W_{src1}$ xor $W_{src2}$
& 4 & dst & src1 & src2\\ \hline

\instr{or} &$W_{dst}$&$W_{src1}$&$W_{src2}$&$W_{dst} \leftarrow  W_{src1}$ or $W_{src2}$
& 5 & dst & src1 & src2\\ \hline

\instr{and} &$W_{dst}$&$W_{src1}$&$W_{src2}$&$W_{dst} \leftarrow  W_{src1}$ and $W_{src2}$
& 6 & dst & src1 & src2\\ \hline

\multicolumn{9}{|c|} {\bfseries }
\\\hline

\instr{move} & $W_{dst}$ & $W_{src}$ & & $W_{dst} \leftarrow W_{src}$                              &8&dst&src&0\\ \hline
\instr{not}  & $W_{dst}$ & $W_{src}$ & & $W_{dst} \leftarrow $ not $W_{src}$                       &8&dst&src&1\\ \hline
\instr{sra}  & $W_{dst}$ & $W_{src}$ & & $W_{dst} \leftarrow $ shift\footnotemark[2] right arithmetic\footnotemark[3] of $W_{src}$ &8&dst&src&2\\ \hline
\instr{srl}  & $W_{dst}$ & $W_{src}$ & & $W_{dst} \leftarrow $ shift\footnotemark[2] right logical of $W_{src}$    &8&dst&src&3\\ \hline

\multicolumn{9}{c} {\bfseries } \\
\hline \multicolumn{9}{|c|} {\bfseries Jump instructions} \\ \hline

\instr{jmp}   & $W_{src}$ & && Jump to $W_{src}$ & 9 & 0 & src & 0\\ \hline
\instr{jmpz}  & $W_{src}$ & && Jump to $W_{src}$ if \textit{zero} & 9 & 0 & src & 2\\ \hline
\instr{jmpc}  & $W_{src}$ & && Jump to $W_{src}$ if \textit{carry} & 9 & 0 & src & 4\\ \hline
\instr{jmpnz} & $W_{src}$ & && Jump to $W_{src}$ if non \textit{zero} & 9 & 0 & src & 3\\ \hline
\instr{jmpnc} & $W_{src}$ & && Jump to $W_{src}$ if non \textit{carry} & 9 & 0 & src & 5\\ \hline
\multicolumn{9}{|c|} {\bfseries } \\\hline

\instr{jmp}   & $W_{src}$ & $W_{ret}$ && Jump to $W_{src}$ & 9 & ret & src & 8\\
&&&& save next address to $W_{ret}$&&&&\\
\hline
\instr{jmpz}  & $W_{src}$ & $W_{ret}$ && Jump to $W_{src}$ if \textit{zero} & 9 & ret & src & 10\\
&&&& save next address to $W_{ret}$&&&&\\
\hline
\instr{jmpc}  & $W_{src}$ & $W_{ret}$ && Jump to $W_{src}$ if \textit{carry} & 9 & ret & src & 12\\
&&&& save next address to $W_{ret}$&&&&\\
\hline
\instr{jmpnz} & $W_{src}$ & $W_{ret}$ && Jump to $W_{src}$ if non \textit{zero} & 9 & ret & src & 11\\
&&&& save next address to $W_{ret}$&&&&\\
\hline
\instr{jmpnc} & $W_{src}$ & $W_{ret}$ && Jump to $W_{src}$ if non \textit{carry} & 9 & ret & src & 13\\
&&&& save next address to $W_{ret}$&&&&\\ 

\hline \multicolumn{9}{c} {\bfseries } \\
\hline \multicolumn{9}{|c|} {\bfseries Load/Store instructions} \\ \hline

\instr{lhi}\footnotemark[4] & $W_{dst}$ & K (8)   && \textit{hi}$(W_{dst}) \leftarrow $ K          & 10 & dst & \textit{hi}(K) & \textit{lo}(K)\\
\hline
\instr{lli}\footnotemark[3] & $W_{dst}$ & K (8)   && \textit{lo}$(W_{dst}) \leftarrow $ K          & 11 & dst & \textit{hi}(K) & \textit{lo}(K)\\
\hline
\instr{lh} & $W_{dst}$ & $W_{src}$ && $W_{dst} \leftarrow $ RAM($W_{src}$)& 8  & dst & src  & 4\\
\hline
\instr{sh} & $W_{src1}$ & $W_{src2}$ && RAM($W_{src1}$) $\leftarrow W_{src2} $ & 12 & 0   & src1 & src2\\

\hline \multicolumn{9}{c} {\bfseries } \\
\hline \multicolumn{9}{|c|} {\bfseries Input/Output - other instructions} \\ \hline

\instr{output} & K (4) & $W_{src}$ && output(K) $\leftarrow W_{src}$      & 13 & 0   & K & src \\ \hline 
\instr{input}  & $W_{dst}$ & K (4) && $W_{dst} \leftarrow$ input(K)       & 8  & dst & K & 5   \\ \hline
\multicolumn{9}{|c|} {\bfseries }
\\\hline
\instr{sleep} &&&&Sleep (see \ref{sleep})                                 & 8 & 0 & 0 & 8\\ \hline

\end{tabular}
\end{center}

\footnotetext[1]{The only difference between \instr{sub} and \instr{subu} is the carry modification (see \ref{carry}).}
\footnotetext[2]{One bit shift. Notice that left shift can be done with \instr{addu} instruction.}
\footnotetext[3]{Arithmetic means that sign bit is copied.}
\footnotetext[4]{Instructions \instr{lli} and \instr{lhi} do not modify or erase the unused part of the register, respectively \textit{hi}$(W_{src})$ and \textit{lo}$(W_{src})$.}

\subsection{Pseudo-instructions}\label{pseudoinstr}

Since real instructions lack some important practical functions, we have created pseudo-instructions. Every time the assembly translator sees such an instruction, this is immediately translated into real instructions.

\begin{warning}
Some pseudo-instructions use $W_{15}$ registers without saving it.
\end{warning}

\begin{center}
\begin{tabular}{|l|l|l|l|l|l|}
\hline \multicolumn{5}{|c|} {\bfseries Load/Store pseudo-instructions} \\ \hline

\instr{li}  & $W_{dst}$ &  K (16)  && \instr{lhi} $W_{dst}$ \textit{hi}(K) \\
                              & & & & \instr{lli} $W_{dst}$ \textit{lo}(K) \\ \hline
\instr{la}  & $W_{dst}$ &label     && \instr{li} $W_{dst}$ addr(label) \\

\hline \multicolumn{5}{c} {\bfseries } \\
\hline \multicolumn{5}{|c|} {\bfseries Arithmetic pseudo-instructions} \\ \hline

\instr{addui}  &$W_{dst}$& K (16) & $W_{src}$ & \instr{li}  $W_{15}$  K  \\
                                       & & & & \instr{addu} $W_{dst}$ $W_{15}$ $W_{src}$ \\ \hline
\instr{adduci}  &$W_{dst}$& K (16) & $W_{src}$ & \instr{li}  $W_{15}$  K  \\
                                       & & & & \instr{adduc} $W_{dst}$ $W_{15}$ $W_{src}$ \\ \hline
\instr{subui}  &$W_{dst}$& K (16) & $W_{src}$ & \instr{li}  $W_{15}$ K  \\
                                       & & & & \instr{subu} $W_{dst}$ $W_{15}$ $W_{src}$ \\ \hline
\instr{subi}  &$W_{dst}$& K (16) & $W_{src}$ & \instr{li}  $W_{15}$ K  \\
                                       & & & & \instr{sub} $W_{dst}$ $W_{15}$ $W_{src}$ \\ \hline

\end{tabular}
\end{center}

\section{Assembly translation}
The second step of our project was to create a program able to translate assembly language into microprocessor instructions (16 bits integers). The program has also a simulation mode, which enable the user to overview the content of the register through the time, so that they can fix their programs.

\subsection{Getting started}
Like for the simulator, you may compile the assembly translator by Code Blocks or our own makefile (just type \texttt{make}). You will then be able to use the program ``asm'' with the following syntax :
\cbox{
asm [options] sources \\
asm -h \textit{for help}
}
Where option are :\\
\texttt{-v} for verbose mode\\
\texttt{--sim} to launch the simulation after asembly translation\\
\texttt{--rc} to display the content of the registers during simulation\\
\texttt{-p} 0 period of one cycle\\
\texttt{-n} 0 maximum number of cycles\\
\texttt{--watch} display a watch instead of just printing the contents of outputs (see bellow)\\

In the watch mode, output ports 0 to 5 corresponds to a 7-segment digits (each bit is a segment - the order is the traditional order : less significant bit is the upper segment). The simulator display the watch each time you wrote something in output port 0. That's why you have to update this port at the end, when you want to update the watch. Please see example "tests/watch.asm" for more informations.

Notice that targets Makefile are nearly the same as simulator ones. You can so automatically run tests by typing : \texttt{make demo TEST=yes}. This will run simulator one each ``*.asm'' file of folder ``tests'' for 1000000 cycles and compare the results with ``*.res'' file.

\subsection{Quick tour of the program code}
Here is a brief description of the way the assembly translator works. We hope it will be helpful if you ever have to look up the source code.\\
\subsubsection{Parsing}
The file is first parsed in the \underline{parser} module. A simple handmade loop gets the arguments and the name of the instructions. A counter stores the number of instructions already studied so that the parser stores with every label name the number of the instruction it corresponds to. Pseudo-instructions may increment the counter more than once because they may introduce a lot of new real instructions. All those instructions are stored in a vector.

\subsubsection{Handling of instructions}
A \underline{map} module stores the main informations about instructions and pseudo-instruction by enabling the creation of a table associating to every string name a special structure.

\bclass{typedef struct instr\_info}{
	\textbf{instr\_type type;}
		 \textit{Instructions are sorted by type to enable global verifications}\\
	\textbf{int code;}
		\textit{The code is the first of the 4 bits of the instruction code in the ROM}\\
	\textbf{int exn;}
		\textit{See below}\\
	\textbf{int nb\_int\_arg;}
		\textit{Number of expected registers or integer constants in the arguments.}
}
The purpose of \textit{exn} is double : A positive exn is the complementary identification of the instruction, that is to say the fourth of 4 bits of the instruction code in the ROM if this bit is used to describe the instruction. \\
A negative \textit{exn} (case of pseudo-instructions) contains the number of real instructions this instruction stands for. \\

The \underline{map} module provides the general structure of the instruction, but the \underline{parser} builds a specific object for every different instruction :


\bclass{class instruction}{
friend class src\_file;\\

\underline{private :}\\
\textbf{instr\_type type;}\\
\textbf{int code;}
	\textit{Instruction code (4 bit integer)}\\
\textbf{int instr\_code;}
	\textit{ROM code (16 bit integer)}\\
\textbf{int exn;}\\
\textbf{string name;}\\
\textbf{int arg[3];}
	\textit{The initial int arguments will be completed later to form the 3 last 4 bits part of ROM instruction code}\\
\textbf{string s\_arg;}
	\textit{String argument for instruction dealing with labels}\\
\textbf{int line;}
	\textit{Line in the assembly program to display errors}\\
\textbf{int nb\_int\_arg;}\\

\underline{public :}\\
\textbf{instruction(string name\_, int cline, table\_instr *table);}
	\textit{Constructor from the generic informations}\\
\textbf{void print();}
	\textit{Print name and arguments.}\\
\textbf{void printc()} \{ cout  $<<$ instr\_code $<<$ endl;\};\\
\textbf{void error(string msg);}\\
\textbf{void verif(table\_label *labels, vector$<$instruction$>$ *vect, vector$<$instruction$>$::iterator *it, bool verbose);}
	\textit{See below}\\

\textbf{bool execute(int registers[18], vector$<$instruction$>$::iterator *it, vector$<$instruction$>$::iterator begin, int ram[SIZE\_RAM], unsigned short inputs[NB\_IO], unsigned short output[NB\_IO], bool watch);}
	\textit{See simulation}
}



A simple loop on all the instructions stored in a vector enables to replace labels by the address of the instruction they correspond to, and replace pseudo-instructions by the real instructions they stand for. The ROM code of the instruction is also computed. All of this corresponds to the function \textit{verif}.


\subsubsection{Simulation}
The simulation of assembler in C++ has to simulate several aspects of the real microprocessor. RAM, input and outputs are represented by tables (integer or short). So are the registers. Note that carry and zero are the $16^{th}$ and $17^{th}$ elements being used to simulate carry and zero register. \\
The actual simulation is executed by calling the \textbf{execute(...)} function of every instruction in the vector. It reacts differently based on the code and arguments of the function, simulating all the operations required.


\subsection{Syntax}
The assembly language recognized is very close to the syntax of microprocessor instructions. Below stands an example of the syntax used.
\cbox{
label1 :\\
label2 : \hspace*{12pt} $instr$ $arg_1$ $arg_2$ $arg_3$\\
\hspace*{50pt} $instr$ $arg_1$ $arg_2$ $arg_3$ ; comments
}
Instructions begin after a tabulation, and are separated of labels by colons. You can add comments after a semicolon. $instr$ is the string corresponding to the name of the real or pseudo-instructions in section \ref{instrset} page \pageref{instrset}. $arg_i$ are most of the time registers names, but they can also be constant integers, or label names. \\
You can find detailed examples in the \textit{.asm} files of our project (``tests'' folder). Here are a few examples of complete instructions.
\cbox{
\hspace*{50pt} 	addui W5 W5 1\\
\hspace*{50pt} 	sub W15 W5 W6\\
\hspace*{50pt} 	la W15 watch
}

\subsection{Watch example}
Thanks to this translator, we were able to program a digital watch in assembly language, in order to run it on our microprocessor. You may find the code of the program in the \textit{tests/watch.asm} file. \\
You can directly simulate the watch with the command :
\cbox{
make watch
}
The result will be printed with the 7-segment interface we introduced before.

There is also a watch which count the time from 23:59:59 to 00:00:00. Just type :
\cbox{
make watch2
}

\addcontentsline{toc}{section}{References}
\begin{thebibliography}{2}
\bibitem{spim} Assemblers, Linkers, and the SPIM Simulator, \textit{James R. Larus}, \url{http://pages.cs.wisc.edu/~larus/HP_AppA.pdf}, novembre 2009
\end{thebibliography}

\end{document}
