
\documentclass[10pt,a4paper]{article}

\usepackage{ifpdf}

\usepackage{amsmath}
\usepackage{amssymb}

\usepackage[latin1]{inputenc}
\usepackage{xcolor}
\usepackage{graphicx}
\usepackage{fullpage}
\usepackage[french]{babel} 
\usepackage[T1]{fontenc} 

\usepackage{ifpdf}

\ifpdf
\usepackage[pdftex, pagebackref=true, colorlinks=true, linkcolor=black, unicode]{hyperref}
\else
\usepackage[ps2pdf, pagebackref=true, colorlinks=true, linkcolor=blue, unicode]{hyperref}
\fi 


\definecolor{border}{rgb}{0.3,0.3,0.3}
\definecolor{fonce}{rgb}{0.5,0.5,0.5}
\definecolor{fond}{rgb}{0.9,0.9,0.9}
\definecolor{b_class}{rgb}{0.0,0.25,0.1}
\definecolor{class}{rgb}{0.9,1,0.95}

\usepackage{varwidth}

\newcommand{\cbox}[1]{
	\vspace{8pt}
	\begin{center}%
	\fcolorbox{border}{fond}{%
	\begin{varwidth}{\textwidth}%
	\textit{#1}%
	\end{varwidth}%
	}%
	\end{center}%
}
\newcommand{\lbox}[1]{
	\vspace{8pt}
	\fcolorbox{fond}{fonce}{%
	\begin{varwidth}{0.4\textwidth}%
	#1%
	\end{varwidth}%
	}%
}
\newcommand{\bclass}[2]{
	\begin{flushright}%
	\textcolor{b_class}{\\ Class : \textbf{#1}} \\%
	\fcolorbox{b_class}{class}{%
	\begin{minipage}{0.8\textwidth}%
	#2%
	\end{minipage}%
	}%
	\end{flushright}%
	\vspace{5pt}
}

\newcommand{\tab}[0]{
	\hspace{8pt}
}


\title	{	
		\normalsize Digital System - I \\
		\huge 	\textbf{Netlist Simulator}
		} 
\date{\small 2009-2010 : Semestre 1}
\author{Fabrice Ben Hamouda, Yoann Bourse, Hang Zhou}

\begin{document}
\maketitle
\tableofcontents
\newpage

This paper describes the first step toward the simulation of a digital watch. The final result will be based on a microprocessor that we will have created, and which will require a netlist simulator, that is to say a program able to interpret and simulate logical circuits.

\section{Simulator overview}
\subsection{Global description}
This simulator was built in C++, mainly because this project immediately appeared to us under the form of classes and pointers. Since the beginning, for purposes of performance, we wanted our simulator to have two main modes : interpreting the data or compiling it. In the following sections, you will see how we translated circuits into text, how we treated this text by C++ programs and how we configured the two modes of output.

\subsection{Netlist language}
We chose to use a language to describe netlists similar to the one displayed in the examples given in the description of the project. The main motivations for this choice were the clearness and the simpleness of the given language. Moreover we wanted to ease the reading of our work by the writer of the project's description. Finally, this syntax presented obvious advantages for the declaration of variables and user-defined functions. You can see below an example of our syntax being used. Note that there are a few technical specificities for practical purposes : the use of the keyword inst, the fact that a closed bracket \} cannot be followed by anything. But you may skip as many lines as you want between functions.\\
Note that our simulator is based on the following set of logical basic instructions which provide a base to the boolean algebra : NOT, OR, AND, XOR, and the register. Register and negation have higher priority than the binary operations, and \textbf{there are no other priority rule}, so use brackets in order to avoid interpretation errors. Default interpretation is from left to right.
\cbox {\\
s,r = FullAdd(a,b,c)\{\\
 s = a\^\ b\^\ c\\
 r = (a \& b) | ((a\^\ b) \& c)\\
\}\\
\# Commentaries can be added by \#\\
\# \^\ means logical XOR\\
\# \& means logical AND\\
\# | means logical OR\\
\\
o = clk2()\{	\\
 o=Z(c)\\
 c=\~\ Z(o)\\
\}\\
\# \~\ means logical NOT\\
\# Z represents a register\\
\# Note that the brackets \{\} are used to introduce a customized function which can be used later with the label "inst", meaning that you instantiate an occurrence of such a circuit.\\
\\
b,c = example (a1,a2,a3)\{\\
 inst b,c = FullAdd(a1,a2,a3)\\
\}
}
We will also have to specify the value of several input variables. The syntax we chose is similar to an array whose columns are separated by a tabulation. It is possible to reproduce a line a certain amount of times using the symbol *, or skip a cycle by an empty line (therefore every empty line creates a new cycle with no forced modification). You may also try to force the value of a variable that is not an input. It will take this value of the beginning of the cycle but may be overwritten by some other functions. Below stands an example :
\cbox {\\
\begin{tabular}{lll}
a1 & a2 & a3 \\ 
0 & 0 & 1 \\ 
0 & 1 & 0 \\ 
$*$5 &  &  \\ 
1 & 1 & 0 \\ 
\end{tabular} 
}

\subsection{Files, classes and main functions}

\subsubsection{Input files}
\begin{itemize}
\item \textbf{input.net}\\
This files contains the netlist description of the used circuits. You must define custom circuits before instantiating them.\\
\item \textbf{input.set}\\
This files contains the default number of clock cycles, and the values of customized variables for each cycle.\\
\end{itemize}

\subsubsection{Programming}
\begin{itemize}

\item \textbf{main}\\
This file is the core of the simulator, as in any C++ project. It loads the various modules (described below) whenever needed. It defines the two possible ways to use the simulator : the compilation or the interpretation. It is also in this file that while loops represent clock cycles.\\

\item \textbf{tools}\\
Here are defined several tools, especially to manipulate vectors more easily.\\

\item \textbf{parserVar}\\
This module creates an item of the settingfile class which can be seen as a flow to read the file "settings.net". 
\bclass{settingfile}{
The variable \textbf{s} contains the source file under the form of a stream.\\
\textbf{Variable repeat} record the number of line repetitions yet to come.\\
\textbf{init\_settings} initializes the global settings at the beginning of the program.\\
\textbf{forced\_var} is a function called every cycle in order to define the value of given variables.
}

\item \textbf{parserNetlist}\\
This file analyses input.net. The parser uses \textbf{step} variables to memorize its position in the syntax analysis : (\textit{see the doxygen documentation for more informations})
\cbox{
Creating a function : \\
0 -outputs- = 1 -function's name- (2 -inputs-)  3 -waiting for the bracket- \{\\
4 -function core- \\
\}\\
\\
Instantiating a function : \\
-1 : no instantiating function\\
-2 : receive output of non instantiating function
}

The function \textbf{ReadFunction} analyses the text of a function : il calls the functions \textbf{ProcessExpression} which analyses a logical expression, and the functions \textbf{ProcessName} which are the core of the creation of the various functions. They are all subfunctions of \textbf{ParserNetList}, which handles as well the topological sort of the functions thanks to the subfunction \textbf{SortlistOps}.\\

\item \textbf{graph}\\
The name of this file is due to the graph structure induced during the parsing, whose consequences are present all over the program.
\bclass{variable}{
This class represents a variable, identified by a \textbf{name and a value}. We register the list of operations of which the variable is an input and we define several functions to read or modify the variable's parameters.
}
\bclass{registerV}{
This class is our mean to deal with the problem of registers : every registerV contains \textbf{two pointers towards "input" variable and "output" variable} : the function \textbf{SaveRegister()} loads the value of the input and the function \textbf{NextClockEdge()} copies it into the output. The \textbf{internal value of the register} allows an easy instantiation of functions : only registers are copied, not the combinatorial graph.
}
\bclass{operation}{
An operation is the heart of a function. Every object of this class contains \textbf{two variable* arrays pointing to the inputs and outputs} of the operation, and a \textbf{functionInst pointer} heading towards the function the operation is used in.
}

\item \textbf{functionUser}
\bclass{functionUser}{
This class is the global one, defining every user-customized function of which the various circuits will be an instance. It contains global parameters shared by all instances of a function such as \textbf{input, outputs, registers} and \textbf{the list of operations sorted topologically}.
} 

\item \textbf{functionInst}
This is a leftover of a previous version of our project, still accessible through the flag \texttt{{-}{-}nogc} \textit{(no graph copy)}. Previously, functionUser was nothing but a generic pattern, and real circuits were instances of functionInst, which used the pattern in order to compute. Yet, this system had a major problem with combinatorial loops when the output of a function was connected to one of its inputs, even through a register. In order to correct that shortcoming, we decided that a circuit would not be an instance of functionInst, but a copy of functionUser to the general functionUser which represent the whole circuit. 
\end{itemize}


\subsection{Executable file and flags}
We allowed the use of flags in order for the user to set various option or parameters when calling the executable file resulting from the compilation of our simulator. Following syntaxes are accepted :
\cbox {simulateur [options] netlist\\
simulateur -h (for help and a total list of possible flags)
}
where main options are :\\
\texttt{-v} : displays comments about what the program is doing (verbose)\\
\texttt{-q} : hides the simulation results\\
\texttt{-p period} : length of a clock cycle (in seconds)\\
\texttt{-c} : compiling mode instead of interpreting\\
\texttt{{-}{-}cc bin} : use "bin" compiler instead of gcc
\texttt{-s settings} : path to the setting file\\
\texttt{-n n} : number of cycles\\
\texttt{{-}{-}column s} : size of a column\\
\texttt{netlist} : path to the netlist file\\
\texttt{{-}{-}noits} : no intermediate toposort (only final)\\

\subsection{Interpreting or compiling ?}
The compiling mode transforms the given circuit in a C program : sim.C and then compiles it. This way, the circuit is an independent program and therefore a lot faster. On the other hand, it is impossible to specify or to force the value of variables with a setting file. Here is an overview of the two processes :\\
\\
\textbf{\underline{Compiling}} :\\
- Variables declaration (\textit{CPutDeclarations})\\
- Combinatorial computing (\textit{CPutCommands}) whole users functions are copied, not only registers.\\
- Save of registers (\textit{CPutRegistersSave})\\
- Next clock, restoring registers (\textit{CPutRegistersNext})\\
 \\ 
\textbf{\underline{Interpreting}} :\\
Every time an operation invoilving a user-created function is called : \\
- Next clock, restoring registers (\textit{NextClockEdge})\\
- Combinatorial computing (\textit{Eval})\\
- Save registers (\textit{SaveRegisters})\\

Note that as mentioned above, there is no longer several user-created functions : they are all embedded in a global function representing the overall circuit, according to the following scheme.

\subsection{Functioning scheme}

\begin{center}
\includegraphics[width=0.6\textwidth]{schema.jpg} 
\end{center}



\newpage
\section{Makefile \& Compilation}

\subsection{Getting started}

On Linux, open a command line console and type :
\begin{itemize}
\item \texttt{make 12345}
\item \texttt{make watch} : you will see a watch without microprocessor
\end{itemize}

To use compiling mode, you need GNU gcc compiler.\\
On Linux, just add option \texttt{SIM\_NS\_FLAGS=-c}.\\
Note that with \texttt{{-}{-}cc} option you can specify options to gcc, for example optimization option like \texttt{-O3} or \texttt{-O2}.

If you want, you can use CodeBlocks : \url{http://www.codeblocks.org}.
There is a CodeBlocks project. Just open it.

\subsection{Targets and options}

We have created a Makefile to automatically compile the project and transform all *.php files (\textit{automatic generation of complex netlists, see 4.5}) into netlist *.net files and to simulate them using if possible *.mem and *.set files.
Important targets are :
\begin{itemize}
\item \texttt{all} : compile the project
\item \texttt{doc} : compile this documentation
\item \texttt{doxygen} : compile the doxygen documentation
\item \texttt{demo} : execute all netlist
\item \texttt{12345} : execute required for project (Full Adder, Minus, ...) netlist
\item \texttt{watch} : print the watch (add some options to simulator to select the good period and the watch output format)
\item \texttt{netlists/\%.run} : execute the netlists/\%.net or netlists/\%.php netlist
\item \texttt{democlean} : delete all generated netlists
\item \texttt{clean} : delete all generated files except documentation and "simulateur" executable
\item \texttt{mrproper} : delete all generated files without any exception
\end{itemize}

There are a lot of options, you can see the Makefile to have more informations :
\begin{itemize}
\item \texttt{TEST=yes} : compare results of simulation with saved results (in *.res files)
\item \texttt{TEST=res} : automatically generate *.res files (you have to verify that the content is correct)
\item \texttt{SIM\_FLAGS} : flags for simulator
\item \texttt{SIM\_NS\_FLAGS} : flags for simulator for target that do not use a setting file (we use it for testing the compilation mode : \texttt{SIM\_NS\_FLAGS=-c})
\end{itemize}

\subsection{Requirements and troubleshooting}
In order for the makefile to work correctly, you will need to have installed support of \textbf{PHP}.

\subsection{Speed of simulator}
To have an approximative idea of the speed of our simulator, you can execute the watch without forcing the period : 
\begin{itemize}
\item \texttt{time make netlists/watch.run SIM\_FLAGS="-n 1000000 {-}{-}watch"}
\item \texttt{time make netlists/watch.run SIM\_FLAGS="-n 1000000 {-}{-}watch -c"}
\end{itemize}
The \texttt{time} command print the time needed to execute the simulation. You can see that compiling mode is faster than interpreting mode. There is an overhead at the beginning because of time of compilation but after that it is very fast. In addition, for real tests, it's recommended to print nothing to stdout (because it takes a lot of time) with flag \texttt{-q} for simulator and to use clock cycles.

\newpage
\section{Simulation results}
\subsection{Theoretical considerations about required set of tests}

For the following circuits, at each cycle $t \in \mathbb{N}$, we call state the list $(z_1(t),...z_m(t))$ of values of output of registers $(z_k)$ at the beginning of the cycle. At each cycle, inputs ($i_1(t),...,i_n(t)$) and state completely define the value of others variables since others variables only depend on value of inputs and of output of registers. In particular, state and inputs define outputs (let's set $(o_1(t),...,o_r(t))$ be the vector of output value at cycle $t$) and next output of registers $(z_1(t+1),...,z_m(t+1))$ because the next output of a register is exactly current value of input of this register. More precisely, there is one function $f$ :
\[
	f : \lbrace0,1\rbrace^{n+m} \rightarrow \lbrace0,1\rbrace^{r+m}
\]
so that the following condition is true :
\[
	(o_1(t),...,o_r(t),z_1(t+1),...,z_m(t+1)) = f(i_1(t),...,i_n(t),z_1(t),...,z_m(t))
\]
States are initialized that way :
\[
	(z_1(0),...,z_m(0))=(0,...,0)
\]
We notice that if inputs are constants (or if there is no input), $\vec{z}(t+1) = (z_1(t+1),...,z_m(t+1))$ only depends on $\vec{z}(t) = (z_1(t),...,z_m(t))$ and on the constant inputs. Since there are only $2^m$ possibilities for the values of a vector in $\lbrace0,1\rbrace^{m}$, the sequence $(\vec{z}(t))_{t \in \mathbb{N}}$ is periodic with a period less or equal than $2^m$. In addition, if at cycle $t$ and cycle $t'$ ($t' \neq t$), states are identical, the period is less than $t'-t$.

In particular, you can notice that if $\vec{z}(t)=\vec{z}(t+1)$ for an cycle $t$, the state is never modified when the circuit is in the state $\vec{z}(t)$ and when input is $i(t)$.

\subsection{Full Adder}
\cbox {\\
\begin{tabular}{l|l|l}
s,r = FullAdd(a,b,c)\{\\
 s = a\^\ b\^\ c\\
 r = (a \& b) | ((a\^\ b) \& c)\\
\}\\
& 
\begin{tabular}{lll}
\\
a & b & c \\ 
0 & 0 & 0 \\ 
0 & 0 & 1 \\ 
0 & 1 & 0 \\ 
0 & 1 & 1 \\ 
1 & 0 & 0 \\ 
1 & 0 & 1 \\ 
1 & 1 & 0 \\ 
1 & 1 & 1 \\ 
$*$9 \\ 
\end{tabular} 
&
\lbox {
Simulation results : \\
\begin{tabular}{lll}
& s & r \\ 
0 & 0 & 0 \\ 
1 & 1 & 0 \\ 
2 & 1 & 0 \\ 
3 & 0 & 1 \\ 
4 & 1 & 0 \\ 
5 & 0 & 1 \\ 
6 & 0 & 1 \\ 
7 & 1 & 1 \\ 
$\cdots$ \\
\end{tabular}
}
\end{tabular}
}
This circuit doesn't involve any register : any output will require no more than one clock cycle in order to be computed. Therefore, we only need to try all the possible combinations for a, b and c (provided by magic masks).



\subsection{Minus}
The minus function is equivalent to negate the input and then add one to it. This means that the first 1 (the least important one) will keep the value 1. All the 0 before will not change, and after it, 0 will be turned into 1 and 1 into 0. That's the property we will have to check on our circuit.\\
$...100\underline{1}00 \rightarrow$ negation : $...011\underline{0}11 \rightarrow$ incrementing : $...011\underline{1}00$ \\
In order to prove this function, we modified the netlist so as to print the output of the register (the only state of the circuit). As long as input is $x=0$, the state $c$ is $0$ (constant input). An input $x=1$ changes the state $c$ to 1 and output $y=1$. After that, all bit are changed to their opposite and that never changes the state $c$ (because $c(2)=c(3)=1$ for input $x=0$ and $c(3)=c(4)=1$ for input $x=1$). We have therefore proved correctness of the circuit with the 5 first lines of simulation results.

\cbox {\\
\begin{tabular}{l|l|l}
y,c = minus\_b(x)\{\\
	y = x \^\ c\\
	c = Z(x|y)\\
\}\\
& 
\begin{tabular}{l}
\\
x \\ 
0 \\
1 \\
1 \\
0 \\
1 \\ 
$*$12\\
\end{tabular} 
&
\lbox {
Simulation results : \\
\begin{tabular}{lll}
& y & c\\ 
0 & 0 & 0 \\  
1 & 1 & 0 \\  
2 & 0 & 1 \\  
3 & 1 & 1 \\ 
4 & 0 & 1 \\  
$\cdots$ \\ 
\end{tabular} 
}
\end{tabular} 
}



\subsection{Counter modulo 2}
We need to check that the counter only counts clock cycles when x=1, and that $s+2r$ corresponds to the number of such cycles, modulo 2. With complete simulation, you can see that when the input is $x=0$, this do not change the state (because $s(0)=s(1)=0$ and $s(2)=s(3)=0$). Hence the number of cycle with input 0 between two cycles with input 1 has no importance. There is only left to verify that, in all states ($s=0$ or $s=1$), when input is 1, counter increments itself (s being the main digit and r the overflow carry) and it is the case. The 5 first lines of simulation results are sufficient to prove correctness of the circuit.


\cbox {
\begin{tabular}{l|l|l}
s,r = cm2(x)\{\\
	s = Z(x \^\ s)\\
	r = x \& s\\
\}\\
& 
\begin{tabular}{l}
\\
x \\ 
1 \\
0 \\
0 \\ 
1 \\ 
0 \\ 
1 \\ 
$*$11\\
\\
\\
\\
\end{tabular} 
&
\lbox {
Simulation results : \\
\begin{tabular}{lll}
& r & s \\ 
0 & 0 & 0 \\  
1 & 1 & 0 \\  
2 & 1 & 0 \\  
3 & 1 & 1 \\  
4 & 0 & 0 \\  
5 & 1 & 1 \\  
6 & 0 & 0 \\  
7 & 1 & 1 \\  
$\cdots$\\ 
$\cdots$\\ 
\end{tabular} 
}
\end{tabular} 
}


\subsection{Clock divider}
This circuit doesn't need any input (only the specification of the number of clock cycles to execute). we need to verify that it produces a periodic output. Hence, we just need to check $2^2=4$ values to be sure that it is a clock divider : first 4 lines are enough.


\cbox {\\
\begin{tabular}{l|l|l}
o = clk2()\{\\
	o=Z(c)\\
	c=\~\ Z(o)\\
\}\\
& 
\begin{tabular}{l}
$*$16\\
\end{tabular} 
&
\lbox {
Simulation results : \\
\begin{tabular}{lll}
& o \\ 
0 & 0 \\  
1 & 1 \\  
2 & 1 \\  
3 & 0 \\  
4 & 0 \\  
5 & 1 \\  
6 & 1 \\  
7 & 0 \\  
8 & 0 \\  
$\cdots$\\ 
\end{tabular} 
}
\end{tabular} 
}


\subsection{Counter modulo 24}
This counter is based on a counter modulo $32=2^5$ that is to say 5 CM2 in a row.  We used the fact that the CM2 contain actually two different numbers : the current number in outputs $s_{i}$ and the next number to come, in $z_{i}$, just before the register. The difficulty to this counter is to reset the outputs when the counter reaches 24. We decided to use an additionnal feedback condition able to reset all $s_{i}$, that is to say that we intercept the future number to come when it is $\ldots0011000 = 24$ and replace it with $\ldots00000 = 0 [24]$. 

  \vspace{60px} 
 \includegraphics[width=\textwidth]{cm24.jpg}
  \vspace{20px}  
For purposes of legibility, we detailed the first part of the input (that is to say \textit{1 / *23 / 0 / *5}).
\cbox {\\
\begin{tabular}{l|l|l}
s,r,z = cm2m(x,v)\{\\
	z = x \^\ s\\
	s = Z(z) \& v\\
	r = x \& s\\
\}\\
\\
s5,s4,s3,s2,s1 = cm24(y)\{\\
	tt = \~\ (z4 \& z5)\
	inst s1,r1,z1 = cm2m(y,tt)\\
	inst s2,r2,z2 = cm2m(r1,tt)\\
	inst s3,r3,z3 = cm2m(r2,tt)\\
	inst s4,r4,z4 = cm2m(r3,tt)\\
	inst s5,r5,z5 = cm2m(r4,tt)\\
\}\\
& 
\begin{tabular}{l}
x\\
1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\1\\
0\\0\\0\\0\\0\\
1\\
$*$27
\\ \vspace{50px} \\ 
\end{tabular} 
&
\lbox {
Simulation results : \\
\begin{tabular}{llllll}
& s5 & s4 & s3 & s2 & s1 \\ 
0 & 0 & 0 & 0 & 0 & 0 \\  
1 & 0 & 0 & 0 & 0 & 1 \\  
2 & 0 & 0 & 0 & 1 & 0 \\  
3 & 0 & 0 & 0 & 1 & 1 \\  
4 & 0 & 0 & 1 & 0 & 0 \\  
5 & 0 & 0 & 1 & 0 & 1 \\  
6 & 0 & 0 & 1 & 1 & 0 \\  
7 & 0 & 0 & 1 & 1 & 1 \\  
8 & 0 & 1 & 0 & 0 & 0 \\  
9 & 0 & 1 & 0 & 0 & 1 \\  
10 & 0 & 1 & 0 & 1 & 0 \\  
11 & 0 & 1 & 0 & 1 & 1 \\  
12 & 0 & 1 & 1 & 0 & 0 \\  
13 & 0 & 1 & 1 & 0 & 1 \\  
14 & 0 & 1 & 1 & 1 & 0 \\  
15 & 0 & 1 & 1 & 1 & 1 \\  
16 & 1 & 0 & 0 & 0 & 0 \\  
17 & 1 & 0 & 0 & 0 & 1 \\  
18 & 1 & 0 & 0 & 1 & 0 \\  
19 & 1 & 0 & 0 & 1 & 1 \\  
20 & 1 & 0 & 1 & 0 & 0 \\  
21 & 1 & 0 & 1 & 0 & 1 \\  
22 & 1 & 0 & 1 & 1 & 0 \\  
23 & 1 & 0 & 1 & 1 & 1 \\  
24 & 1 & 0 & 1 & 1 & 1 \\  
25 & 1 & 0 & 1 & 1 & 1 \\  
26 & 1 & 0 & 1 & 1 & 1 \\  
27 & 1 & 0 & 1 & 1 & 1 \\  
28 & 1 & 0 & 1 & 1 & 1 \\  
29 & 0 & 0 & 0 & 0 & 0 \\  
30 & 0 & 0 & 0 & 0 & 1 \\  
31 & 0 & 0 & 0 & 1 & 0 \\  
$\cdots$\\ 
52 & 1 & 0 & 1 & 1 & 1 \\  
53 & 0 & 0 & 0 & 0 & 0 \\  
$\cdots$\\ 
\end{tabular} 
}
\end{tabular} 
}

\newpage
\section{Further Improvements}
\subsection{Diagram display}
\begin{center}
 \includegraphics[width=0.9\textwidth]{diag.jpg} 
\end{center}
To improve the legibility of the outputs, we have imagined another display of the output : instead of 0 and 1, the \textbf{{-}{-}diag} flag causes the output to be a frieze where 0 is bottom and 1 is top, as displayed on the example.
\subsection{The time parameter}
In order to simulate the quartz periodic signal for the microprocessor, we have decided to allow the user to set the duration they want for a clock cycle. This is done thanks to an additional loop and the use of the function gettime of day.
\subsection{Boolean constants}
We added the possibility to use boolean constants 0 and 1 directly in the netlist, therefore avoiding the need to declare an alimentation like VDD.
\subsection{RAM/ROM primitives}
As a transition toward the work that is simulating a whole microprocessor, we have added to our project ROM/RAM primitives. You can instantiate ROM or RAM with the following code :
\cbox {ram $d_{o1},d_{o2} = name (a_{o2},a_{o1},a_{o0},w,a_{i2},a_{i1},a_{i0},d_{i1},d_{i0})$\\
rom $d_{o1},d_{o0} = name (a_{o2},a_{o1},a_{o0}) $\\
\\
First character : Data or Address \\
Second character : In or Out, that means for writing (in) or for reading (out)\\
Third character : level of bit (2 being the most significant bit)\\
w : write input data into input address if equal to 1
}
Size of address bus and data bus are determined by the number of arguments and returned values. More precisely, if there are $n$ returned values and $m$ arguments, data bus is $n$ bits length and address bus is $m-n$ bits length for ROM and $\frac{m-n-1}{2}$ bits length. The order of argument is this mentioned above. Size of memory is $2^a$ if address bus has $a$ bits. Names of variables have no importance.

Reading is executed before writing. You can also define RAM and ROM through a \textit{*.mem} file using the flag : \texttt{-m file}. The content of the file should follow that pattern, with the keyword \textbf{mem} : 
\cbox {mem:Name\\
3\\
2\\
12\\
mem:Name2\\
...
}
This uses a special functionInst called \textbf{functionMem}, which stores the data in a \textbf{data} vector.


\subsection{Circuit-based digital watch}
The conclusion of this simulation work was the simulation of a digital watch based on complex circuits as describes in the courses provided by Mr Vuillemin. The netlists of those gigantic circuits were created thanks to \textbf{PHP scripts} which offered a very clear way to display text in loops or recursive calls. It offered a nice transition towards the microprocessor-based digital watch, with for instance the creation of a graphic interface based on 7-segments display, activated by the flag \textbf{{-}{-}watch}. This subject will be later discussed in our next report.


\section{Doxygen documentation}
A detailed documentation is available in the folder \textit{"doc"}, describing more precisely every file, class and function. Just type \texttt{make doxygen} to compile it.

\end{document}